Publications

[DAC'25] Han Wang, Ming Tang^†, Quancheng Wang, Ke Xu, Yinqian Zhang

ZenLeak: Practical Last-level Cache Side-Channel Attacks on AMD Zen Processors

Design Automation Conference, San Francisco, 2025.06

[TACO] Quancheng Wang, Ming Tang^†, Ke Xu, Han Wang

Unveiling and Evaluating Vulnerabilities in Branch Predictors via a Three-Step Modeling Methodology

ACM Transactions on Architecture and Code Optimization, 2025.01

[TC] Ke Xu, Ming Tang^†, Quancheng Wang, Han Wang

Microarchitectural Attacks and Mitigations on Retire Resources in Modern Processors

IEEE Transactions on Computers, 2024.12

[DATE'24] Han Wang, Ming Tang^†, Ke Xu, Quancheng Wang

Cache Bandwidth Leaks Secrets

Design, Automation and Test in Europe Conference, 2024.03

[HPCA'24] Quancheng Wang, Ming Tang^†, Ke Xu, Han Wang

Modeling, Derivation, and Automated Analysis of Branch Predictor Security Vulnerabilities

International Symposium on High-Performance Computer Architecture, 2024.03

[HPCA'24] Ke Xu, Ming Tang^†, Quancheng Wang, Han Wang

Exploitation of Security Vulnerability on Retirement

International Symposium on High-Performance Computer Architecture, 2024.03

[JSA] Yuzhe Gu, Ming Tang^†, Quancheng Wang, Han Wang, Haili Ding

One more set: Mitigating conflict-based cache side-channel attacks by extending cache set

Journal of Systems Architecture, 2023.11

[SCN] Han Wang, Ming Tang^†

Cross-Core and Robust Covert Channel Based on Macro-op Fusion

Security and Communication Networks, 2023.04

[Arxiv] Quancheng Wang, Ming Tang^†, Han Wang, Yuzhe Gu

BackCache: Mitigating Contention-Based Cache Timing Attacks by Hiding Cache Line Evictions

Arxiv, 2023.04

[TC] Ke Xu, Ming Tang^†, Han Wang, Sylvain Guilley

Reverse-Engineering and Exploiting the Frontend Bus of Intel Processor

IEEE Transactions on Computers, 2022.11